A peak hold circuit shown in FIGS. 1 and 2 and known in the art is used for generating an output signal that is in accordance with a peak value (maximum value) of an input signal.
In a peak hold circuit 150 shown in FIG. 1, an input signal Vin, which is a voltage signal, is provided to an inversion input terminal of an operational amplifier 151. An output terminal of the operational amplifier 151 is coupled to a gate of a P-channel MOS transistor Q30 functioning as a charge pump.
The source of the transistor Q30 is coupled to a high potential power supply VDD, and the drain of the transistor Q30 is coupled to ground via a capacitor C serving as a hold capacitor. A current source 152, which controls the droop rate (reduction rate) of the hold voltage for the capacitor C, is coupled in parallel to the capacitor C. A node N between the transistor Q30 and the capacitor C is coupled to an output terminal of the peak hold circuit 150 via a buffer circuit 153. The peak value of the input signal Vin held in the capacitor C is output from the output terminal as the output signal Vout.
In the peak hold circuit 150, the transistor Q30 is activated when the input signal Vin becomes higher than the hold voltage of the capacitor C (potential of the node N), and the capacitor C is charged by the charging current flowing to the capacitor C. The charging of the capacitor C is stopped when the hold voltage of the capacitor C becomes equal to the voltage of the input signal Vin. When the voltage of the input signal Vin becomes lower than the voltage of the capacitor C, the transistor Q30 is inactivated and the capacitor C is uncoupled from the operational amplifier 151. This holds the present hold voltage of the capacitor C, that is, the peak value of the input signal Vin, and the peak voltage is output from the output terminal as the output signal Vout. When the input signal Vin again becomes higher than the hold voltage of the capacitor C, the transistor Q30 is activated, the capacitor C is charged, and the peak value is updated. Therefore, the operational amplifier 151 and the transistor Q30 form a feedback loop in the peak hold circuit 150, and the input signal Vin and the output signal Vout (hold voltage of the capacitor C) are constantly compared. The accuracy of the peak detection is thus high. The hold voltage of the capacitor C is gradually discharged by a droop current Id of the current source 152 during the hold period.
In a peak hold circuit 160 shown in FIG. 2, the input signal Vin, which is a voltage signal, is provided to a base of an input transistor Q31, which is an NPN transistor. The collector of the input transistor Q31 is coupled to a high potential power supply VDD, and the emitter is coupled to ground via a capacitor C1 serving as a hold capacitor A current source 161 for controlling the droop rate of the hold voltage of the capacitor C1 is coupled in parallel to the capacitor C1. A node N1 between the input transistor Q31 and the capacitor C1 is coupled to a non-inversion input terminal of an operational amplifier 166.
The output signal of the operational amplifier 166 is provided to a base of a correction transistor Q32, which is an NPN transistor, and also output from the output terminal of the peak hold circuit 160 to an external circuit (not shown) as the output signal Vout. The collector of the correction transistor Q32 is coupled to the high potential power supply VDD, and the emitter is coupled to ground via a current source 167. A node N2 between the correction transistor Q32 and the current source 167 is coupled to the inversion input terminal of the operational amplifier 166. The operational amplifier 166, the correction transistor Q32, and the current source 167 function as a correction circuit 165 for correcting the hold voltage of the capacitor C1 to substantially the same potential as the peak value of the input signal Vin.
In the peak hold circuit 160, when the input signal Vin is input to the input transistor Q31, the capacitor C1 is charged to a potential lower than the voltage of the input signal Vin by an amount corresponding to a forward voltage of a diode (formed between base-emitter of the input transistor Q31). The diode is inactivated when the potential difference between the input signal Vin and the hold voltage of the capacitor C1 (potential of the node N1) becomes lower than the forward voltage of the diode. In this case, the capacitor C1 is not charged, and the capacitor C1 is uncoupled from the input transistor Q31. This holds the present voltage of the capacitor C1 as the hold voltage. However, the hold voltage of the capacitor C1 is lower than the peak value of the input signal Vin by an amount corresponding to the forward voltage of the diode. Therefore, a correction circuit 165 corrects the hold voltage of the capacitor C1 to be substantially the same potential as the peak value of the input signal Vin and then outputs the corrected voltage as the output signal Vout. In other words, a node N1 and a node N2 are controlled to have the same potential by the feedback loop, which is formed by the correction transistor Q32 having the same element size as the input transistor Q31 and the operational amplifier 166. The base voltage of the transistor Q32 then becomes higher than the voltage of the node N2 (voltage of the node N1) by an amount corresponding to the forward voltage of the diode. As a result, the hold voltage of the capacitor C1 is corrected to have substantially the same potential as the peak value of the input signal Vin and is output as the output voltage Vout.
In this manner, in an analog circuit in which the amplitude of the input signal is not constant, the peak hold circuits 150 and 160 detect the envelope of the input signal or optimize the gain of the amplification circuit by detecting the peak value of the input signal. Thus, the peak hold circuit is used in various types of circuits. Japanese Laid-Open Patent Publication No. 5-126869 describes such a peak hold circuit.
However, the peak hold circuits 150 and 160 have the shortcomings described below.
To detect a peak, the peak hold circuit 150 shown in FIG. 1 needs to compare the input signal Vin and the previous peak value (hold voltage of the capacitor C) and activate the transistor Q30 with a signal that is in accordance with the comparison result. Thus, such feedback loop requires a relatively long time to charge the capacitor C. Such feedback loop limits the response characteristics (e.g., of the operational amplifier 151). Thus, the peak value cannot be held in an ensured manner if the input signal Vin is a high-speed signal. Specifically, if the input signal Vin is a high-speed signal, the period in which the input signal Vin becomes greater than the hold voltage of the capacitor C, that is, the ON period of the transistor Q30 becomes relatively short. In this case, if the timing for activating the transistor Q30 is delayed due to the feedback loop, the charging time of the capacitor C is shortened, and the peak detection operation ends before holding the peak value of the input voltage Vin. As a result, the peak value of the input signal Vin cannot be held in an ensured manner.
In the peak hold circuit 160 shown in FIG. 2, the response speed is fast since the peak is detected by a simple circuit configuration formed by the transistor Q31 and the capacitor C1. Therefore, the peak hold circuit 160 is suitable for high-speed operations However, since the hold voltage of the capacitor C1 is lower than the peak value of the actual input signal Vin by an amount corresponding to the forward voltage of the diode of the transistor Q31, the accuracy of peak detection is low. To improve the accuracy, the correction circuit 165 shown in FIG. 2 corrects the hold voltage of the capacitor C1 by compensating for the difference of the amount corresponding to the forward voltage of the diode. However, in the peak hold circuit 160, a difference occurs in the base-emitter voltages of the transistors Q31 and Q32 since the bias conditions are not the same in the input transistor Q31 and the correction transistor Q32. This lowers the accuracy of the hold voltage corrected by the correction circuit 165. This directly affects the output signal Vout and consequently lowers the accuracy of peak detection.
Such problems are not limited to a peak hold circuit that holds the maximum value of the input signal Vin and also arise in a peak hold circuit that holds the minimum value (peak value) of an input signal.